Rotate operations are common functions performed in the execution unit of a microprocessor and other circuits. Each of the rotate instructions shifts the bits of the specified register or memory operand ("source operand"). In the case of a microprocessor that executes the 486 instruction set, shift logic is used in implementing rotate operations such as rotate left/right (ROL/ROR) and rotate through carry left/right (RCL/RCR).
The ROL (rotate left) instruction shifts all of the bits of the source operand left by one or more positions, with the most significant bits shifting around and becoming the least significant bits. The ROR (rotate right) instruction performs the rotate operation in the opposite direction. It shifts all bits to the right by one or more positions, with the least significant bits shifting around and becoming the most significant bits.
The RCL and RCR (rotate carry left and right) instructions use a carry flag as part of the rotation process for rotating the source operand. The RCL instruction shifts the carry flag into the least significant bit and shifts the most significant bit into the carry flag. Similarly, the RCR instruction shifts the carry flag into the most significant bit and shifts the least significant bit into the carry flag.
The rotate instruction includes a second operand, which may be either the contents of a register or an immediate number, specifying the number of positions to shift the source operand. This rotation count can be anywhere between zero and thirty-one. Only the five least significant bits of the rotation count are used.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: in an .times.86 type microprocessor, an improved shifter design capable of performing left/right rotate operations based on operand size (i.e., 8, 16, and 32 bit) while reducing the complexity of the shift matrix logic.
For a conventional 32 bit .times.86 type microprocessor architecture, a conventional rotate matrix design would have to include multiplexing logic capable of performing rotates based on operand size. Specifically, for rotate operations, the shift matrix would receive a 32 bit input with 1-4 bytes of valid data. The specified rotate operation would then be performed by appropriately shifting and multiplexing the data byte in response to a five bit shift count, an operand size indication and associated control information. There is considerable complexity to this multiplexing logic and associated control to implement all of the various rotate operations.
Accordingly, a specific object of the invention is to provide an improved shifter design in which multiplexing logic is less complex.